Amplifier uses are perverse in the electronics industry. One such use is sense amplifiers in memory arrays. Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. A predetermined number of cells are located in rows between each of a plurality of upper and lower word lines and another predetermined number of cells are located in columns between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
A row of cells is selected when a high voltage is supplied to the appropriate word line. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly to the sense amplifier. A second read current through the other bit line flows through one side of the memory cell. When a cell is written, the first write current is directed into one side of the cell and the second write current is directed out of the cell.
In most memory arrays using NMOS or CMOS memory cells, sensing data quickly becomes difficult due to the large capacitance associated with the common bit line nodes. To achieve fast sensing, this capacitance must be charged or discharged quickly to produce a voltage differential large enough at the common bit lines, or the gain of the sense amplifier must be high enough, to sense small voltage changes at the common bit line nodes.
Techniques commonly used to achieve sufficient speed for sensing include multiple block memory arrays which reduce the common bit line capacitance and multiple stage sense amplifiers which increases the overall gain of the sense amplifier circuit. However, the multiple block memory arrays provides increased area on chip and circuit complexity, and multiple stage sense amplifiers create longer read access delays.
Thus, what is needed is a transimpedance amplifier having high open loop gain, low input impedance and an input clamped by feedback that minimizes input signal voltage excursions in the presence of large capacitances.